ume: Add interpolation to rv64ume and custom template tags by arcane-quill · Pull Request #834 · OpenVADL/openvadl

arcane-quill · 2026-03-22T16:50:22Z

PR for issue #757 (and #761, #759)
interpolated hardcoded rv64ume files from linux-user
created UmeHardcodedRiscvDefinitionPass and UmeTemplateRenderingPass to add custom template tags (e.g. registers, exceptions..) with hardcoded values that later get filled in by the vadl file
added VIAM definition UserModeEmulation

flofriday · 2026-03-22T17:14:36Z

I think the branch of this PR isn't cleanly based on a fresh master, because it contains some of my commits that are already on master.

So let's rebase on master with (on your branch):

git fetch
git rebase origin/master

There might be some conflicts but if you execute these commands in IntelliJ you'll get some help resolving the conflicts in a nice UI. 😉

arcane-quill · 2026-03-22T18:15:43Z

I think the branch of this PR isn't cleanly based on a fresh master, because it contains some of my commits that are already on master.

So let's rebase on master with (on your branch):
git fetch
git rebase origin/master
There might be some conflicts but if you execute these commands in IntelliJ you'll get some help resolving the conflicts in a nice UI. 😉

I tried to rebase twice now but it doesnt seem to be fixed @flofriday

flofriday · 2026-03-22T18:26:53Z

Yeah sometimes rebasing still contains some weired artifacts, but I just tried it on my machine and it (mostly) worked. I'll send you a DM (on matrix), let's figure it out there.

Jozott00

Unfortunately the current state is too RISC-V specific and needs an overhaul. Please take a closer look at other VIAM definitions and how they are handled in the code emission.

arcane-quill · 2026-04-14T09:02:12Z

Unfortunately the current state is too RISC-V specific and needs an overhaul. Please take a closer look at other VIAM definitions and how they are handled in the code emission.

Thanks for the extensive review, I'm working on it now

arcane-quill · 2026-05-09T10:55:48Z

hi @Jozott00 I resolved the stuff that was missing, hopefully we can get this merged now

and do u know why passorders keeps telling me there is a merge conflict despite none of it showing up locally, even after rebasing?

flofriday · 2026-05-09T14:54:44Z

and do u know why passorders keeps telling me there is a merge conflict despite none of it showing up locally, even after rebasing?

Mostly guesses here but I assume you are not syncing your local branches with the remote (GitHub).

For example

git rebase master

Isn't good enough to rebase with the newest changes from GitHub.
This is mostly because master on your machine isn't updated and is stuck on an old commit.

The long way is to do:

git checkout master
git pull # (download from the remote, and also update the current master branch to the newest version from the remote)
git checkout <your-branch>
git rebase master

But you can even shorten this a bit with

git fetch # Downloads the branches from the remote but does not update the local branches only the branches prefixed with origin will be updated, so master is still stuck on an old commit but origin/master is synced with the remote
git rebase origin/master

Jozott00

I think there are still some important things to change. Mostly, what and how the VIAM definition stores specification details.

I also think, that we should reduce the scope for the PR a bit, as signals are just a bit too much to start with. Therefore, let's completely remove all logic that is related to signals.

The UME generation requires quite a bit of information from the ABI definition and could share some constructs (like alias registers and special register references). Therefore, I will do a little ABI refactoring, so you can use RegisterRef instead of defining you own RegisterLocation as mentioned in a comment below.

EDIT: Also note, that this PR won't fully close #761 as there is still RISC-V specific stuff in the template files.

Jozott00 · 2026-05-11T08:37:03Z

+  private final ExceptionDef breakpointExcName;
+  private final ExceptionDef illegalInstrExcName;
+  private final Identifier initialPc;
+  private final Identifier initialSp;


question: What is the initialPC and initialSp? Can you give me an example, cause I am confused how its value can be represented as Identifier.

From what I understand, this can be removed, as it can be synthesized later by the generator.

Jozott00 · 2026-05-11T10:09:57Z

-    env->pc = regs->sepc;
-    env->x[RV64UME_REG_SP] = regs->sp;
+    env->[(${pc_reg.name_lower})] = regs->[(${config.initialPc})];
+    env->[(${config.mainRegisterFile})][ [(${config.spReg})] ] = regs->[(${config.initalSp})];


major: As we just hardcode the target_pt_regs anyway, just use regs->pc and regs->sp instead.

@Jozott00 can I add pc to the struct? else it will always give me this error " ‘struct target_pt_regs’ has no member named ‘pc’; did you mean ‘sepc’?" for regs->pc

Jozott00 · 2026-05-11T10:12:14Z

minor: This whole table is currently hardcoded. However, I think we should do the dynamic interpolation in a separate PR.

…` interface (#948) This PR extracts most of the `Abi.RegisterRef` to `vadl.viam.RegisterRef`, so the datastructure can be reused in other definitions like the UME (#834). Additionally, it removes the `GeneratesRegisterFileName` which does not fit into the VIAM hierarchy and is already covered by the `RegisterResource` class.

Jozott00

Your branch is currently conflicting with origin/master. This is because we moved the ISS PassOrder construction to IssPassOrder.

Additionally there are still some issues from the last review that were not addressed yet.

Also please test the generated QEMU, I think at the PR's current state, the generated QEMU wouldn't work.

Jozott00 · 2026-06-03T08:29:41Z

+    alias register a0  = X(10)
+    alias register a1  = X(11)
+    alias register a2  = X(12)
+    alias register a3  = X(13)
+    alias register a4  = X(14)
+    alias register a5  = X(15)
+    alias register a6  = X(16)
+    alias register a7  = X(17)
+    alias register sp  = X(2)
+    alias register ra  = X(1)
+    alias register gp = X(3)
+    alias register fp   = X(8)
+
+    return address    = ra
+    stack  pointer    = sp
+    return value      = a0
+    frame pointer     = fp
+    global pointer    = gp
+    function argument = a{0..7}
+    caller saved = [ a{0..7} ]
+    callee saved = [ ra, fp,
+                     X(9),  X(18), X(19), X(20), X(21),
+                     X(22), X(23), X(24), X(25), X(26), X(27) ]
+
+    special absolute address load instruction = LA
+    special local address load instruction   = LLA
+
+    special return instruction = RET
+    special call instruction = CALL


Fine for now, later this should be minimized to a minimal set of definitions that is required for the UME (#968).

Jozott00 · 2026-06-03T11:47:48Z

+  private final InstructionSetArchitecture isa;
+  private final Abi abi;
+
+  private final List<RegisterUtils.Register> args;


major: You are still using the LCB template RegisterUtils instead of the RegisterRef as added in #948.

Yea I'm having issues here because my local master branch won't properly update (to pull in the RegisterRef), so I think I'd need to rebase, but I'm behind quite a few commits and I'm worried I'll mess up the history

You should be able to merge origin/master into your feature branch.
I will squash this PR during merge, so the branch-local commit history doesn't really matter.

Okay, I'll do a merge of master into this branch instead of a rebase then

Jozott00 · 2026-06-03T11:50:04Z

+    Map<String, Integer> excIds = Map.of(
+        "ILLEGAL_INSTR", 2,
+        "ECALL", 11,
+        "BREAKPOINT", 3
+    );


major: This is still hardcoded. However, it should be obtained from the VIAM instead.

should I remove this, since we agreed on the synthetic exception anyway?

Yes, you can remove it. You can also skip illegal_instr and breakpoint handling for now.

Jozott00 · 2026-06-03T11:52:50Z

+        .orElseThrow(() -> new IllegalStateException("No UserModeEmulation defined"));
+
+    Abi abi = ume.abi();
+    RegisterTensor mainRegFile = (RegisterTensor) abi.stackPointer().registerFile();


major: This is not the right abstraction. In theory each syscall related register could originate from a different register file (or no "register file" at all). So you can't just assume that there is one RegisterTensor that includes all registers that are used for the syscall.

Jozott00 · 2026-06-03T11:56:51Z

+    );
+
+    vars.put("config", Map.ofEntries(
+        Map.entry("sysReg", abi.stackPointer().addr()),


major: You assign the SP as sysReg, which I assume to be wrong.

Jozott00 · 2026-06-03T11:59:37Z

+
+  private final List<RegisterUtils.Register> args;
+  private final Instruction syscallInstr;
+  private final ExceptionDef syscallException;


major: I think with the discussion summary #950 (comment), the UME definition shouldn't have an ExceptionDef anymore.

The exception used in QEMU under the hood is a synthetic one.

Jozott00 · 2026-06-03T12:01:16Z

+    RegisterTensor.Dimension regDim = new RegisterTensor.Dimension(
+        0,
+        Type.bits(5),
+        32
+    );
+
+    RegisterTensor.Dimension dummyDim = new RegisterTensor.Dimension(
+        1,
+        Type.bits(1),
+        1
+    );
+
+    List<RegisterTensor.Dimension> dimensions = List.of(regDim, dummyDim);
+    RegisterTensor mainFile = new RegisterTensor(
+        new Identifier(new String[]{"x"},
+            SourceLocation.INVALID_SOURCE_LOCATION),
+        dimensions
+    );


major: This should come from the passed ISA, and shouldn't be created here.

Jozott00 · 2026-06-03T12:02:18Z

+    ExceptionDef mockSyscallExc = new ExceptionDef(
+        new Identifier(new String[]{"EXC"},
+            SourceLocation.INVALID_SOURCE_LOCATION),
+        emptyParams,
+        emptyGraph,
+        ExceptionDef.Kind.DECLARED
+    );
+
+    ExceptionDef mockBreakpointExc = new ExceptionDef(
+        new Identifier(new String[]{"BREAKPOINT"},
+            SourceLocation.INVALID_SOURCE_LOCATION),
+        emptyParams,
+        emptyGraph,
+        ExceptionDef.Kind.DECLARED
+    );
+
+    ExceptionDef mockIllegalExc = new ExceptionDef(
+        new Identifier(new String[]{"ILLEGAL_INSTR"},
+            SourceLocation.INVALID_SOURCE_LOCATION),
+        emptyParams,
+        emptyGraph,
+        ExceptionDef.Kind.DECLARED
+    );


major: Either obtain them from the ISA or remove them (if they are not part of the current VADL spec)

Jozott00 · 2026-06-03T12:03:24Z

+    Function mockFunc = new Function(
+        new Identifier(new String[]{"dummy_function"},
+            SourceLocation.INVALID_SOURCE_LOCATION),
+        new Parameter[0],
+        Type.string(),
+        emptyGraph
+    );
+
+    Assembly emptyAssembly = new Assembly(new Identifier(new String[]{"dummy_assembly"},
+        SourceLocation.INVALID_SOURCE_LOCATION), mockFunc);
+
+    Format dummyFormat = new Format(new Identifier(new String[]{"dummy_format"},
+        SourceLocation.INVALID_SOURCE_LOCATION), mockType);
+
+    Encoding emptyEncoding = new Encoding(
+        new Identifier(new String[]{"dummy_encoding"},
+            SourceLocation.INVALID_SOURCE_LOCATION),
+        dummyFormat, new Encoding.Field[0]);
+
+    Instruction mockSyscallInsn = new Instruction(
+        new Identifier(new String[]{"ECALL"},
+            SourceLocation.INVALID_SOURCE_LOCATION),
+        emptyGraph, emptyAssembly, emptyEncoding
+    );


major: Should also be obtained from the ISA and not created here.

#757

arcane-quill · 2026-06-08T13:01:50Z

I'm retrieving the args from the ABI now, is it fine like this?

Jozott00 · 2026-06-08T13:45:14Z

I'm retrieving the args from the ABI now, is it fine like this?

You mean the syscall argument registers? Those must come from the UME definition and can't be taken from the ABI, as in general, the ABI argument registers and the syscall argument registers are not the same.

arcane-quill · 2026-06-08T14:00:04Z

I'm retrieving the args from the ABI now, is it fine like this?

You mean the syscall argument registers? Those must come from the UME definition and can't be taken from the ABI, as in general, the ABI argument registers and the syscall argument registers are not the same.

right but since I only have the ABI right now, I was thinking it might be a bit cleaner than using the hardcoded version, but I can also revert it back to the way it was to avoid confusion

Jozott00 · 2026-06-08T14:02:14Z

I think for now you should create the register references the hardcoded way. However, don't create the X register tensor itself.

arcane-quill requested a review from Jozott00 March 22, 2026 16:50

arcane-quill self-assigned this Mar 22, 2026

github-actions Bot added lcb This is LCB related frontend This is frontend related iss This is ISS related labels Mar 22, 2026

This was linked to issues Mar 22, 2026

ume: Define VIAM definitions for the UME VADL specification #757

Open

ume: Add pass to add a hardcoded UserModeEmulation VIAM definition #759

Open

ume: Parameterize QEMU templates and render them using the VIAM #761

Open

arcane-quill force-pushed the wip/ume-viam-def branch 2 times, most recently from ce9eaf4 to 0d64625 Compare March 22, 2026 19:08

arcane-quill changed the title ~~Wip/ume viam def~~ ume: Add interpolation to rv64ume and custom template tags Mar 23, 2026

arcane-quill force-pushed the wip/ume-viam-def branch from 2c3616b to 4d6afb8 Compare March 23, 2026 00:41

arcane-quill force-pushed the wip/ume-viam-def branch 2 times, most recently from 4d6afb8 to f54e597 Compare April 4, 2026 02:18

arcane-quill force-pushed the wip/ume-viam-def branch 2 times, most recently from 4d6afb8 to f54e597 Compare April 12, 2026 01:50

flofriday reviewed Apr 13, 2026

View reviewed changes

Comment thread vadl/main/vadl/ast/AstVisitor.java

Jozott00 requested changes Apr 14, 2026

View reviewed changes

arcane-quill requested a review from Jozott00 May 9, 2026 10:55

Jozott00 requested changes May 11, 2026

View reviewed changes

Jozott00 mentioned this pull request May 11, 2026

viam: Extract Abi.RegisterRef and remove GeneratesRegisterFileName interface #948

Merged

Jozott00 requested changes Jun 3, 2026

View reviewed changes

github-actions Bot added the hardware Related to the MiA and hardware generation label Jun 3, 2026

arcane-quill and others added 21 commits June 3, 2026 19:13

ume: Add interpolation and specific pass for ume template tags #757

cef416f

ume: Add specific tags for regs and exceptions #757

33bf7f8

ume: Fix subdir in meson

95cdeb5

ume: Add interpolation and specific pass for ume template tags #757

2a65a6c

ume: Remove everything related to frontend #757

8749792

ume: Add ume definition #757

275af19

ume: Add more values for interpolation #757

f9870ad

ume: Add missing interpolation #757

fec5dc8

ume: Fix checkstyle violations #757

fc5e22e

ume: Fix more checkstyle violations #757

1440cb7

ume: Remove duplicate line #757

28c1e59

ume: Revert frontend changes #757

3f37df9

ume: Revert atg file changes #757

3f7de33

ume: Use proper viam objects and fix templates #757

b6d7912

ume: Revert misc file

488a431

#757

ume: Fix signal.c reigster handling #757

8c54fa7

ume: Add ifs for causevar and signal to template #757

5fde96b

ume: Refactor UME definitions #757

dcb3847

ume: Add UME section to vadl file, remove exceptions from cpuloop #757

daec0b8

ume: Add syscall section to vadl file #757

a6a88bf

iss: Fix UME pass order

1379c83

Jozott00 force-pushed the wip/ume-viam-def branch from 5c4264c to 1379c83 Compare June 3, 2026 17:20

ume: Fix registers #757

53fbd00

arcane-quill added 2 commits June 12, 2026 18:47

ume: Use hardcoded arguments #757

4f2a2ec

ume: Improve register hardcoding #757

16ea90b

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